1. Field of the Invention
The present invention relates to a semiconductor integrated circuit using BiCMOS techniques for fabricating a MOS transistor and a bipolar transistor on the same chip and, more particularly, to a semiconductor logic circuit suitable for high-speed operation.
2. Description of the Background Art
FIG. 31 shows a typical selector circuit of prior art as described in Neil H. E. Weste, Kamran Eshraghian, "Principles of CMOS VLSI Design", see page 202. In FIG. 31, MP1 to MP6 designate PMOS transistors; MN1 to MN6 designate NMOS transistors; VI1 designates a first input terminal; VI2 designates a second input terminal; VI3 designates a third input terminal; VI4 designates a fourth input terminal; VOUT1 designates a first output terminal; VDD designates a first power supply of 5.0 V; GND designates a second power supply of 0 V; and CL1 designates a first load capacity. The transistors MP1 and MN1 form a first inverter circuit INV1, and the transistors MP2 and MN2 form a second inverter circuit INV2. The first and second inverter circuits INV1 and INV2 serve as a buffer circuit for a signal inputted to the input terminal VI1. Similarly, the transistors MP3 and MN3 form a third inverter circuit INV3, and the transistors MP4 and MN4 form a fourth inverter circuit INV4. The third and fourth inverter circuits INV3 and INV4 serve as a buffer circuit for a signal inputted to the input terminal VI2. The PMOS transistors MP5, MP6 and the NMOS transistors MN5, MN6 form a pass transistor circuit PT1.
Operations of the selector circuit of FIG. 31 will be described below. A high level signal provides a voltage of 5.0 V, and a low level signal provides a voltage of 0 V. A threshold between the high and low logical levels is 2.5 V. The inverted signal of a signal to be applied to the third input terminal VI3 is applied to the fourth input terminal VI4. The PMOS transistor that has a threshold voltage of -0.5 V turns on when the voltage of the gate electrode thereof is lower than that of the source electrode thereof by 0.5 V or more. The NMOS transistor that has a threshold voltage of 0.5 V turns on when the voltage of the gate electrode thereof is higher than that of the source electrode thereof by 0.5 V or more. When a low level signal is applied to the third input terminal VI3, the NMOS transistor MN5 turns off, and the PMOS transistor MP5 turns off since a high level signal is applied to the fourth input terminal VI4 whereas the PMOS transistor MP6 and the NMOS transistor MN6 turn on. At that time, if a high level signal is applied to the input terminal VI2, the PMOS transistor MP3 turns off and the NMOS transistor MN3 turns on, so that the inverter circuit INV3 outputs a low level signal. Since the input of the inverter circuit INV4 is at the low level, the NMOS transistor MN4 turns off and the PMOS transistor MP4 turns on, so that the load capacity CL1 of the output terminal VOUT1 is charged up to the power supply voltage VDD (5.0 V) through the PMOS transistor MP6 and the NMOS transistor MN6. Thus the output terminal VOUT1 is at the high level. If a low level signal is applied to the input terminal VI2, the PMOS transistor MP3 turns on and the NMOS transistor MN3 turns off, so that the inverter circuit INV3 outputs a high level signal. Since the input of the inverter circuit INV4 is at the high level, the NMOS transistor MN4 turns on and the PMOS transistor MP4 turns off, so that the load capacity CL1 of the output terminal VOUT1 is discharged to the GND voltage (0 V) through the PMOS transistor MP6 and the NMOS transistor MN6. Thus the output terminal VOUT1 is at the low level.
When a high level signal is applied to the third input terminal VI3, the NMOS transistor MN5 turns on, and the PMOS transistor MP5 turns on since a low level signal is applied to the fourth input terminal VI4 whereas the PMOS transistor MP6 and the NMOS transistor MN6 turn off. At that time, if a high level signal is applied to the input terminal VI1, the PMOS transistor MP1 turns off and the NMOS transistor MN1 turns on, so that the inverter circuit INV1 outputs a low level signal. Since the input of the inverter circuit INV2 is at the low level, the NMOS transistor MN2 turns off and the PMOS transistor MP2 turns on, so that the load capacity CL1 of the output terminal VOUT1 is charged up to the power supply voltage VDD (5.0 V) through the PMOS transistor MP5 and the NMOS transistor MN5. Thus the output terminal VOUT1 is at the high level. If a low level signal is applied to the input terminal VI1, the PMOS transistor MP1 turns on and the NMOS transistor MN1 turns off, so that the inverter circuit INV1 outputs a high level signal. Since the input of the inverter circuit INV2 is at the high level, the NMOS transistor MN2 turns on and the PMOS transistor MP2 turns off, so that the load capacity CL1 of the output terminal VOUT1 is discharged to the GND voltage (0 V) through the PMOS transistor MP5 and the NMOS transistor MN5. Thus the output terminal VOUT1 is at the low level.
The circuit of FIG. 31 is a two-input selector circuit responsive to the signal applied to the third input terminal VI3 for selectively outputting either the signal applied to the input terminal VI1 or the signal applied to the input terminal VI2. Transistors responsive to the signal applied to the gate electrode for transmitting or cutting off the signal inputted to the source (or drain) electrode such as the PMOS transistors MP5, MP6 and the NMOS transistors MN5, MN6 are referred to as pass transistors.
In the conventional semiconductor integrated circuit having the aforesaid arrangement, the inverter circuit INV2 or INV4 charges and discharges the load capacity CL1 through the pass transistor circuit PT1 to determine the logical level of the output terminal VOUT1. The on-resistance of the inverter circuit INV2 or INV4 and the on-resistance of the pass transistors MP5, MP6, MN5, MP6 forming the pass transistor circuit PT1 are connected in series between the first power supply VDD or the second power supply GND and the output terminal VOUT1. This causes a large resistance of the charging and discharging path of the load capacity CL1 and, as a result, it takes long to determine the logical level of the output terminal VOUT1.